Appeal No. 2006-2832
Application No. 09/833,953
(Examiner’s Answer, page 4). Looking closely at Erdeljac, Figure 11, we observe
that field oxide region 20 clearly extends through the transistor gate region over the
N well and under the resistors. The teaching of the claimed limitation “said field
oxide region not being situated over said well” is not within the teaching of
Erdeljac, Zaccherini or Shao.
The rejection of claims 1, 3 to 12 under 35 U.S.C. § 103(a) is thus reversed.
Elements of the Claim: Claims 14, 15 and 17 to 23
Claim 14 is exemplary of this group of claims, recited supra. Though
Appellant indicates that claim 14 recites “similar limitations as independent claim
1” discussed above (Brief, page 16), the claim is distinguishable for
reciting “depositing a polycrystalline silicon layer on a chip, said polycrystalline
silicon layer including a gate region and a resistor region, said gate region being
situated over a well and said resistor region not being situated over said well,
wherein said field oxide region and said well are situated in a substrate….”
Continuing the analysis used with claim 1 above, applied now to claim 14,
we note in Erdeljac, in Figure 11, a resistor region containing resistors 32, 34, 56
and transistor gate region 24 over N well 18, with the resistor region not being
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