Ex Parte Racanelli - Page 4



            Appeal No. 2006-2832                                                                            
            Application No. 09/833,953                                                                      


                   14. A method comprising steps of:                                                        
                   depositing a polycrystalline silicon layer on a chip, said polycrystalline               
            silicon layer including a gate region and a resistor region, said gate region being             
            situated over a well and said resistor region not being situated over said well,                
            wherein said field oxide region and said well are situated in a substrate;                      
                   forming a doping barrier above said polycrystalline silicon layer after said             
            step of depositing said polycrystalline silicon layer so as to prevent doping of said           
            resistor region of said polycrystalline silicon layer;                                          
                   doping said polycrystalline silicon layer with a first dose of a first dopant            
            after said step of forming said doping barrier, wherein said dose of said first dopant          
            is a dosage greater than required to result in said layer over said gate region having          
            transistor gate electrical properties, wherein said first dopant has a first                    
            conductivity type;                                                                              
                   removing said doping barrier after said step of doping said polycrystalline              
            silicon layer with said first dose of said first dopant;                                        
                   doping said polycrystalline silicon layer with a second dose of a second                 
            dopant after said step of removing said doping barrier so as to form a high                     
            resistivity resistor in said resistor region of said polycrystalline silicon, wherein           
            said second dopant has a second conductivity type, wherein said first dose of said              
            first dopant is higher than said second dose of said second dopant such that said               
            transistor gate electrical properties are unaffected by said second dose of said                
            second dopant;                                                                                  
                   forming a silicide blocking oxide layer over an inner portion of said                    
            polycrystalline silicon layer over said field oxide region after said step of doping            
            said polycrystalline silicon layer with said second dose of said second dopant;                 
                   doping an outer portion of said resistor region of said polycrystalline silicon          
            layer with a third dopant after said step of forming said silicide blocking oxide               
            layer                                                                                           
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