Appeal 2007-1650
Application 11/111,799
STATEMENT OF CASE
Appellants appeal from a final rejection of claims 20, 21, 23, 26-28,
30, and 332 under authority of 35 U.S.C. § 134. The Board of Patent
Appeals and Interferences (BPAI) has jurisdiction under 35 U.S.C. § 6(b).
An Oral Hearing was held on August 7, 2007.
Appellants’ invention relates to an improved clock signal generator in
an integrated circuit in which the effective speed of the clock signals can be
controlled by either hardware changes or by post-production software
control signals. The programmability allows the manufacturer to speed up
the clock to a point just below where the clock pulses would overlap. In the
words of the Appellants:
During the manufacturing phases of chip production,
characteristics of the on-chip clock generator are altered to ensure the
edges of the two generated clocks do not overlap. This allows the
manufacturer to optimize the performance of the chip while the chip is
undergoing initial production testing. This feature obviates the need
to perform costly and time consuming trial-and-error design and
redesign of on-chip clock generators.
Additionally, the present invention provides a technique for
optimizing the performance of the on-chip clock generator after the
chips have left the manufacturing environment. One feature of the
present invention is the ability to adjust clock generation dynamically
to account for climatic changes in an operational, or other post-
production, environment. This allows chips to be manufactured with
wider tolerances and allows operation of the chip to be optimized
when the chip is in the operational environment.
(Specification 4).
2 Claims 22, 24, 25, 29, 31, and 32 were objected to, and were indicated to be
allowable if put into independent form. (Final Rejection, mailed 3/6/06,
page 4)
2
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