Appeal 2007-1650
Application 11/111,799
Claim 20 is exemplary:
20. A hardware-programmable clock generator for an integrated circuit
chip, comprising:
a clock input portion;
first and second clock outputs;
a first feedback path coupling the first clock output to the clock input
portion;
a second feedback path coupling the second clock output to the clock
input portion; and
a first plurality of switches coupled to the first feedback path, each of
the first plurality of switches configurable during manufacturing to couple a
corresponding one of a first plurality of delay elements in series along the
first feedback path, wherein the coupling of delay elements along the first
feedback path controls the amount of time that clock edges associated with
the first and second clock outputs are non-overlapping.
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Walters, Jr. US 5,041,738 Aug. 20, 1991
(filed Dec. 4, 1989
Rejection:
Claims 20, 21, 23, 26-28, 30, and 33 stand rejected under 35 U.S.C.
§ 102(e) for being anticipated by Walters. Claims 22, 24, 25, 29, 31, and 32
have been objected to, and have been indicated as being allowable if the
limitations of their respective independent and intermediate claims are
included in them. (Final Rejection 4, filed March 6, 2006).
Appellant contends that the claimed subject matter is not anticipated
by Walters for failure of the references to teach limitations in the claims, as
3
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: September 9, 2013