Appeal 2007-1650
Application 11/111,799
the delay elements control the amount of time that those periods of non-
overlap occur. Although the delay elements control periods in which the
outputs overlap, they nevertheless necessarily control periods of non-overlap
as well. We thus do not find error in the rejection for Appellants’ first
reason.
Appellants next argue that “eliminating a transistor in Walters does
not necessarily add or reduce any sort of delay along lines 24 or 26 [the
feedback paths] in Walters …, thus the transistors are not “delay elements”.
(Br. 18, middle). In the footnote at the bottom of the page, Appellants
remind us that a delay element, according to the Specification, may be
“inverters or any device (i.e. resistors) that delay a signal”. (Br. 18 n.1)
Certainly the fuses and associated transistors in Walters are devices, and
their purpose and operation are to cause the respective lagging and leading
of the clock signals by controlled amounts. (Walters, Col. 6, middle). We
find that they can fairly be read on the delay elements.
Finally, Appellants argue that the claim requires “a first plurality of
delay elements in series along the …feedback path”. Pointing to Figure 4 of
Walters, Appellants argue that the delay elements are arranged in parallel,
not in series. (Br. 18 middle). While it is true that the individual elements
are arranged in parallel with each other, the block of them is arranged in
series in the feedback paths 24 and 26, as is readily noticed in Figure 1.
For the foregoing reasons, we conclude that Appellants have not
found reversible error in the rejection of claims 20, 21, 23, 26-28, 30, and
33.
10
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: September 9, 2013