Appeal 2007-1650
Application 11/111,799
input from an external system clock, and then generates two
complementary clock signals for use on the IC. (Specification
4, Figure 2A). The use of these two clock signals permits the
operations on the IC to proceed faster than if they relied solely
on the system clock. To keep operations properly
synchronized, however, it is important that the two clock signal
not overlap each other. Since clock signals degenerate as they
traverse the IC, it is useful to be able to adjust the clock speed
so that the clocks operate as fast as they can, but not so fast that
at any location on the chip the clock signals overlap.
(Specification 3). The invention allows the user to program the
clock speed to achieve this goal, by both hardware means (e.g.
laser burning of delay elements in the clock circuitry to short
them out) and by software means (e.g., control signals to effect
a shorting of the delay elements). (Specification 4 and 5). The
delay elements of each clock generator are placed in the path
where the output of one generator feeds the input of the other.
(Figure 6B).
2. Examiner has rejected the noted claims over the patent to
Walters. Walters teaches placing dual phase clock circuitry on
a Large Scale Integration (LSI) chip “for such logic circuits …
require their own clock generator for generating internal phase
clock signals for their own use.” (Col. 1, ll. 23-25). This
internal clocking can be controlled “for adjusting the clock
overlap voltage either up or down to speed up or slow down a
chip after fabrication. This technique utilizes a laser to break or
5
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: September 9, 2013