Appeal 2007-1650
Application 11/111,799
open up fuses connected to electrodes of transistor devices.”
(Col 1, l. 45ff). In Figure 1 of Walters, there is taught a
generator of two clock signals, in which a variable delay is
introduced in the path where the output of one generator (e.g.
#22) feeds the input of the other generator (e.g., #18). (Figure
1).
3. The clock signals in Walters are shown in Figures 3(a), (b) and
(c), where the amount of overlap of the clock signals is
controlled by the techniques of that patent. In Figure 3(b), “it is
desired to decrease the amount of overlap voltage …, the
plurality of fuses F3a-F3n would be blown initially by a laser
cut…” (col 6, ll. 37-39). “As a result, this produces the
minimal amount of overlap voltage between the trailing or
falling edge of the true phase clock signal Ø1 (curve 36a) and
the leading or rising edge of the complementary phase clock
signal Ø2 (curve 38a).” (Col. 6, ll. 53-57).
PRINCIPLES OF LAW
On appeal, Appellants bears the burden of showing that the Examiner
has not established a legally sufficient basis for the rejection of the claims.
“In reviewing the [E]xaminer’s decision on appeal, the Board must
necessarily weigh all of the evidence and argument.” In re Oetiker, 977
F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992).
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