Appeal No. 1997-2041
Application No. 08/337,131
The patent to Mazzali (Figures 1 and 3) pertains to a non-
volatile buried bit-line EPROM device including a plurality of
memory cells. More specifically, there are a plurality of
doped spaced apart source and drain areas shown in Figure 3 as
elements 2 and 3, respectively. The grown field oxide areas
are represented by elements 5 and 7. The grown tunnel oxide
layer is indicated by elements 4 and 6. Elements 9 in Figure 3
correspond to the formed floating gate members. The formed
insulating layer is represented by element 14 and the formed
control gate layer is represented by element 15, both of which
are shown in Figure 3. Thus, Mazzali teaches the claimed
invention except for: (1) using a monocrystalline silicon
material for the substrate and (2) the step of forming the
floating gate members subsequent to forming the plurality of
source areas and the plurality of drain areas.
At the outset, we note that the use of a monocrystalline
silicon for the material of the substrate represented the
state-of-the-art in the buried bit-line EPROM device art at the
time of the appellant’s invention. This position is further
supported by both Guterman and Woo described below.
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