Appeal No. 1998-2189
Application 08/097,372
data transfer control means for forming and
transmitting a clock signal from the first processor
means to the second processor means, the data transfer
control means including means for asynchronously changing
the clock signal from a first state to a second state
when each bit of a respective one of the plurality of
data values is transferred, and for resetting the clock
signal to the first state after each individual bit of a
data value is transferred, said clock signal being
exclusively driven by the first processor means; and
data transfer means responsive to the direction
signal and the clock signal for transmitting the
plurality of data values between the processors as
indicated by the direction signal.
The Examiner relies on the following references:
Costes et al. (Costes) 4,999,769 March 12, 1991
Bush et al. (Bush) 5,150,465 September 22, 1992
Claims 1-10 and 13 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Bush and Costes.
We refer to the final rejection (Paper No. 8), the
examiner's answer (Paper No. 16) (pages referred to as
"EA__"), and the supplemental examiner's answer (Paper No. 18)
(pages referred to as "SEA__") for a statement of the
Examiner's position, and to the brief (Paper No. 14) (pages
referred to as "Br__") and the reply brief (Paper No. 17)
(pages referred to as "RBr__") for a statement of Appellant's
arguments thereagainst.
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