Appeal No. 1998-2189
Application 08/097,372
register R2, bit 4, described at column 11, lines 17-25.
According to the flex mode description, when written by the
drive 20, registers R2 and R3 contain the least-significant
byte (LSB) and most-significant byte (MSB), respectively, of a
16-bit Operation Status Word (col. 10, lines 59-63). After
registers R2 and R3 are written, an interrupt to the host
adapter 32 is initiated to notify the host, processor 12, that
the status has been updated (col. 11, lines 2-5). Thus, the
DTH and DRQ bits are written by the drive 20 and read by the
processor 12 (Table 3, col. 24); accordingly, processor 34
must be the first processor means and processor 12 must be the
second processor means to be consistent with claim 1.
Column 9 describes a block transfer mode where information,
including the direction of transfer, is written by disk
driving routines on the processor 12 to be read by the
controller 24 (col. 9, lines 31-56). Thus, processor 12 must
be the first processor means and processor 34 must be the
second processor means to be consistent with claim 1. For the
purpose of discussion, we use the disclosure at column 11.
The DTH and DRQ bits in register R2 are written by only
drive 20 containing the first processor means 34. Appellant's
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