Appeal No. 1998-2189
Application 08/097,372
means" to be the microprocessor 34 in the I/O controller 24 of
drive 20 (figures 1 and 2). The Examiner finds that Bush
teaches (EA4):
direction control means for forming and transmitting
a direction signal from the first processor to the second
processor (Abstract; Fig. 2; col. 11, lines 17 - 31);
. . .
Bush clearly discloses a direction signal exclusively
driven by a first processor (processor 12).
Specifically, Bush teaches information that includes
details of the direction of transfer (from host to
peripheral or from peripheral to host) wherein the disk
driving software executed, on the processor, writes "set
up information into appropriate registers 40" (col. 9,
lines 13 - 18, 29 - 44).
We find the Examiner's reasoning inconsistent because
column 11 and column 9 refer to different transfer modes where
the direction is specified by different processors. Column 9
refers to a block-transfer compatible drive operation, whereas
column 11 refers to the "flex mode" drive operation, which can
emulate a variety of different block transfer protocols.
Although the Examiner's explanation is not specific, we agree
with Appellant's interpretation (Br6) of the rejection
referring to column 11 as referring to Bush's DTH (direction
to host) bit, register R2, bit 3, described at column 11,
lines 26-30, and possibly also the DRQ (data request bit),
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