Appeal No. 1998-2189
Application 08/097,372
claim onto Costes, since the two clock signals are not the
same clock signal. The description that adapter 5 "generates"
adapter clock signal 36 (col. 3, lines 40-43, 51-53),
indicates that adapter 5 drives adapter clock signal 36. The
DMA clock signal on line 28 is referred to as a "first clock
signal" and the adapter clock signal on line 36 is referred to
as a "second clock signal" (e.g., col. 1, lines 51-61),
indicating two clock signals. On a very elementary level it
can be seen that the inverted clock signal on line 36 is not
the same signal as the DMA clock signal on line 28 even though
it is derived from the signal on line 28. Thus, we agree with
Appellant that both processors 12 and 5 drive a separate clock
signal. Further, claim 1 requires "said clock signal being
exclusively driven by the first processor means" and "data
transfer means responsive to the direction signal and the
clock signal for transmitting the plurality of data values
between the processors as indicated by the direction signal."
Claim 1 requires the same clock signal to clock data in both
directions, which is not done in Costes (col. 2, lines 4-12).
Thus, we find that Costes does not cure the deficiency of Bush
with respect to the limitation of "said clock signal being
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