Appeal No. 1998-2189
Application 08/097,372
limitation of "[the direction signal] to notify the second
processor means that the first processor means is ready to
transfer data to the second processor means when the direction
signal has a second state" is more problematic. After the
registers R2 and R3 are written by the drive 20, an interrupt
to the host adapter 32 is initiated to notify the host
processor 12 that the status has been updated (col. 11,
lines 2-5). Thus, it appears that the DTH direction bit in
Bush does not perform the recited function of notifying the
second processor means 12. However, since the limitations are
not argued, we do not rely on them. See 37 CFR §
1.192(c)(8)(iv) (1995).
Clock signal
The Examiner finds that "Bush does not explicitly teach
exclusively driven clock signals" (EA4). This statement is
misleading in that "does not explicitly teach" (emphasis
added) suggests that the teaching might be implicit, when, in
fact, Bush is silent about clock signals. The Examiner finds
that Costes discloses a clock signal 28 exclusively driven by
the DMA controller 12, citing column 3, lines 44-53 (EA4-5;
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