Appeal No. 1998-2189
Application 08/097,372
answer that processor 12 is the first processor that controls
the direction of data transfer and the fact that register R2
is written by the disk drive 20. As noted in the preceding
paragraph, processor 12 does not write bits DTH or DRQ in the
flex mode of column 11.
For the reasons discussed in the preceding two
paragraphs, we find that Bush teaches "said direction signal
being exclusively driven by the first processor means."
Appellant has argued only the limitation of "said
direction signal being exclusively driven by the first
processor means" in connection with the "direction control
means." Nevertheless, we note that the Examiner's rejection
does not address or evidence any recognition of the other
limitations of the "direction control means." The limitation
of the "direction signal from the first processor means to the
second processor means, to enable the second processor means
to transfer data to the first processor means when the
direction signal has a first state" could be considered to be
broadly met since the second processor 12 is broadly "enabled"
to transfer data to the first processor 34 (in the
controller 24) when the DTH bit is reset. However, the
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