Appeal No. 1998-2189
Application 08/097,372
exclusively driven by the first processor means" and, for this
reason, the Examiner has failed to establish a prima facie
case of obviousness.
In addition, although not argued, it is not seen how the
clock in Costes could possibly teach the other limitations of
the "data transfer control means," in particular, "the data
transfer control means including means for asynchronously
changing the clock signal from a first state to a second state
when each bit of a respective one of the plurality of data
values is transferred, and for resetting the clock signal to
the first state after each individual bit of a data value is
transferred." We find no discussion or recognition of these
limitations by the Examiner. In Costes, the "clock signal is
synchronous with the data sent from the DMA controller"
(col. 3, lines 49-50). Thus, the clock signal is not
asynchronous as claimed. Furthermore, there is no teaching
that the clock should operate to change states, as claimed, to
transfer data. It appears that the Examiner has merely tried
(unsuccessfully) to find bidirectional data transfer between
two processors using a single clock signal and has ignored the
functional limitations. Nevertheless, since the limitations
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