Appeal No. 1998-2189
Application 08/097,372
argument (Br6) that the contents of the DRQ bit, bit 4, are
not exclusively driven by the first processor 34 because bit 4
is also set by processor 12, referring to column 12,
lines 10-13 and 37-44, is in error. It is true that registers
R1-R10 are written to by both drive 20 and processor 12 as
shown in Table 3 (col. 24), where the middle column indicates
the meaning attached to the register when written by drive 20
and read by processor 12, and the third column indicates the
meaning attached to the registers when written by processor 12
and read by controller 24 containing processor 34. However,
although both processor 12 and processor 34 write to the same
register, the registers have different meanings depending on
which processor does the writing. The status bits DRQ (bit 4)
and DTH (bit 3) in register R2 are written only by drive 20;
when bits 3 and 4 are written by processor 12, they have
different meanings (col. 12, lines 37-45, line 55 (bit 3 is
unused); figure 4c). Thus, we find that processor 12 does not
write a direction signal.
Appellant's argument (RBr5) that two different processors
12 and 34 control the direction to host bit DTH (RBr5) is
apparently based on the Examiner's finding in the examiner's
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