Appeal No. 1998-2189
Application 08/097,372
SEA2). Appellant's note that this is a new point of argument
raised for the first time in the examiner's answer (RBr5).
We agree with Appellant's description of Costes (RBr6).
In Costes, a DMA controller synchro clock signal on line 28 is
generated by DMA controller 12 and is used by adapter 5 to
sample data sent from controller 12 to adapter 5 on the DMA
bus (col. 3, lines 44-52). The adapter 5 generates an adapter
clock on line 36 which is sent to DMA controller 12 and used
to sample the data received from adapter 5 on the DMA bus
(col. 3, lines 40-43 and 54-61). We agree with Appellant's
finding that "the data transfer means of Costes requires two
different clock signals 28 and 36 driven by two different
processors 12 and 5, respectively, to transmit the data values
between the processors in a direction indicated by the
direction signal" (RBr6).
As we understand the Examiner's position, the DMA
controller exclusively drives a clock signal because the clock
signal on line 36 is generated by inverting the received
synchro DMA clock signal on line 28; that is, DMA controller
drives both the DMA clock signal 28 and, indirectly, the
adapter clock signal 36. We disagree with this reading of the
- 10 -
Page: Previous 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Next
Last modified: November 3, 2007