Appeal No. 1999-2256 Page 13
Application No. 08/686,477
resetting said watch dog timer means when said CPU transmits a
bus permission signal to said DMAC for using said bus” or
“timer control means for resetting said watch dog timer means
while said DMAC uses said bus.” Therefore, we reverse the
rejection of claims 4, 5, and 10 and of claim 6, which depends
from claim 4. We proceed to the third group of claims.
III. Claims 11-20
The examiner asserts, “Mager teaches ... transmitting the
count clock signal to the watch dog timer when the CPU
transmits a bus permission signal to the DMAC [27:-1-5].”
(Examiner’s Answer at 5-6.) Regarding claims 11-15, the
appellants argue, “[n]o prior art of record, either alone or
in combination, discloses this concept of the bus permission
signal being received by both the watch dog timer and the DMA
controller.” (Appeal Br. at 12.) Regarding claims 16-20,
they add, “[a]s explained above ... there is or disclosure or
suggestion in the prior art of a bus permission line connected
between a CPU, a DMA controller, and the watch dog timer.”
(Id. at 15.)
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