Appeal No. 1999-2256 Page 9
Application No. 08/686,477
said count clock signal transmitted from a second external
device and transmitting said count clock signal to said watch
dog timer means, and for halting a transmission of said count
clock signal transmitted from an external device to said watch
dog timer means under a condition that said DMAC uses said
bus,” or “a count clock controller for supplying said count
clock signal to said runaway detection circuit, receiving a
bus permission signal from a CPU and halting the supplying of
said count clock signal to said runaway detection circuit when
said bus permission signal is received.” Therefore, we
reverse the rejection of claims 1, 2, 9, and 21 and of claim
3, which depends from claim 1. We proceed to the second group
of claims.
II. Claims 4, 5, 6, and 10
The examiner asserts, “Mager explicitly teaches that
binary counter 2900 (contained in watch dog timer 105) will be
reset upon receipt of a signal by OR gate 3025 on line 104
indicating that a normal condition of a direct memory access
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