Appeal No. 1999-2256 Page 5
Application No. 08/686,477
The examiner asserts, “Mager teaches ... halting [ 27:50,
e.g., ‘indefinite reset’] the supplying of the count clock
signal to the runaway detection circuit when the bus
permission signal is received.” (Examiner’s Answer at 3.)
The appellants argue, “[t]here is simply no disclosure or
suggestion anywhere within Mager et al that the clock signal
is halted ....” (Reply Br. at 2.)
In deciding obviousness, “[a]nalysis begins with a key
legal question -- what is the invention claimed?” Panduit
Corp. v. Dennison Mfg. Co., 810 F.2d 1561, 1567, 1 USPQ2d
1593, 1597 (Fed. Cir. 1987). “Claim interpretation ... will
normally control the remainder of the decisional process.”
Id. at 1567-68, 1 USPQ2d at 1597. Here, claims 1 and 9
specify in pertinent part the following limitations: “count
clock control means for receiving said count clock signal
transmitted from a second external device and transmitting
said count clock signal to said watch dog timer means, and for
halting a transmission of said count clock signal transmitted
from an external device to said watch dog timer means when
said CPU transmits a bus permission signal to said DMAC for
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