Appeal No. 1999-2256 Page 12
Application No. 08/686,477
case of obviousness.” In re Rijckaert, 9 F.3d 1531, 1532, 28
USPQ2d 1955, 1956 (Fed. Cir. 1993)(citing In re Oetiker, 977
F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992)). “If
examination at the initial stage does not produce a prima
facie case of unpatentability, then without more the applicant
is entitled to grant of the patent.” Oetiker, 977 F.2d at
1445, 24 USPQ2d at 1444 (citing In re Grabiak, 769 F.2d 729,
733, 226 USPQ 870, 873 (Fed. Cir. 1985) and In re Rinehart,
531 F.2d 1048, 1052, 189 USPQ 143, 147 (CCPA 1976)).
Here, the examiner fails to identify which of the AND
gates shown in Figure 24 of the reference he believes
discloses or would have suggested an AND gate receiving a
CPU’s control signal and bus permission signal and its
outputting a forced reset signal to a runaway control circuit
when the CPU transmits the bus permission signal or when a
DMAC uses a system bus. We will not “resort to speculation,”
In re Warner, 379 F.2d 1011, 1017, 154 USPQ 173, 178 (CCPA
1967), as to his belief. Accordingly, we are not persuaded
that the teachings from the applied prior art would have
suggested the limitations of “timer control means for
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