Appeal No. 1999-2256 Page 6
Application No. 08/686,477
using said bus by said DMAC.” Similarly, claim 2 specifies in
pertinent part the following limitations: “count clock control
means for receiving said count clock signal transmitted from a
second external device and transmitting said count clock
signal to said watch dog timer means, and for halting a
transmission of said count clock signal transmitted from an
external device to said watch dog timer means under a
condition that said DMAC uses said bus.” Accordingly, the
limitations of claims 1, 2, and 9 require inter alia halting
the supply of a count clock signal to a watch dog timer
because a DMAC is using a system bus.
Claim 21 specifies in pertinent part the following
limitations: “a count clock controller for supplying said
count clock signal to said runaway detection circuit,
receiving a bus permission signal from a CPU and halting the
supplying of said count clock signal to said runaway detection
circuit when said bus permission signal is received.”
Accordingly, the limitations require inter alia halting the
supply of a count clock signal to a runaway detection circuit
because a bus permission signal has been issued by a CPU.
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