Appeal No. 1999-2256 Page 3
Application No. 08/686,477
Responsive to the bus permission signal, the watch dog timer
is stopped and the DMA transfer is done.
Claim 21, which is representative for present purposes,
follows:
21. A watch dog timer device comprising:
a runaway detection circuit for counting a count
clock signal and outputting a reset signal when
overflow is caused; and
a count clock controller for supplying said
count clock signal to said runaway detection
circuit, receiving a bus permission signal from a
CPU and halting the supplying of said count clock
signal to said runaway detection circuit when said
bus permission signal is received.
The prior art applied by the examiner in rejecting the
claims follows:
Richardson et al. (“Richardson”) 4,131,945 Dec. 26, 1978
Mager et al. (“Mager”) 4,137,565 Jan. 30, 1979
Loftis et al. (“Loftis”) 5,185,693 Feb. 9,
1993
Carr, Microprocessor Interfacing 11, 17 (1982).
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007