Appeal No. 1999-2256 Page 14
Application No. 08/686,477
Claim 11 specifies in pertinent part the following
limitations: “issuing a bus permission signal by the CPU;
receiving the bus permission signal by the watch dog timer and
the DMA controller ....” Similarly, claim 16 specifies in
pertinent part the following limitations: “a bus permission
line, different from the control bus, connected between the
CPU, the DMA controller, and the watch dog timer ....”
Accordingly, the limitations of claims 11 and 16 respectively
require inter alia that a DMAC and a watch dog timer both
receive a bus permission signal from a CPU and that a bus
permission line, different from a control bus, connects the
CPU, the DMAC, and the watch dog timer
The examiner fails to allege, let alone show, that
Mager’s “fault watch timer or watch dog timer (WDT) module 105
in the IOPM 90 of FIG. 24,” col. 26, ll. 7-8, receives a bus
permission signal from the reference’s “CPU 40 in the central
processor unit module 120,” col. 4, ll. 29-30, or is connected
thereto by a bus permission line. Accordingly, we are not
persuaded that the teachings from the applied prior art would
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