Appeal No. 1999-2256 Page 11
Application No. 08/686,477
following limitations: “timer control means for resetting said
watch dog timer means while said DMAC uses said bus.”
The appellants’ specification describes the timer control
means as “an AND circuit.” (Spec. at 13) More specifically,
“bus permission signal S5 is supplied to one input terminal of
an AND circuit 74, and then the output from the AND circuit 74
is transmitted to a forced reset terminal R of the runaway
control circuit [72] ....” (Id.) Figure 7 of the
specification, furthermore, shows that a “control signal from
CPU” is supplied to the other input terminal of the AND
circuit. Interpreting claims 4, 5, and 10 in light of the
corresponding structure described in the specification, the
limitations require inter alia an AND gate receiving a CPU’s
control signal and bus permission signal and its outputting a
forced reset signal to a runaway control circuit when the CPU
transmits the bus permission signal or when a DMAC uses a
system bus.
“In rejecting claims under 35 U.S.C. Section 103, the
examiner bears the initial burden of presenting a prima facie
Page: Previous 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Next
Last modified: November 3, 2007