Appeal No. 1999-2256 Page 17
Application No. 08/686,477
AB v. Crucible, Inc., 793 F.2d 1565, 1571, 230 USPQ 81, 84
(Fed. Cir. 1986)).
Here, in the passage of Richardson on which the examiner
relies, a DMA unit suspends operations of a control processor.
Specifically, “a direct memory access unit in a controller is
operative to receive an enabling address signal on a system
bus from a control processor thereby allowing it to issue a
hold signal back to the control processor for operational
suspension thereof.” Col. 2, ll. 7-11. The examiner fails to
show that the control processor outputs a reset signal, let
alone that the DMA unit prevents the control processor from
outputting a reset signal because a bus permission signal has
been issued.
Because there is no showing that Richardson’s DMA unit
prevents the reference’s control processor from outputting a
reset signal because a bus permission signal has been issued,
we are not persuaded that the applied prior art discloses the
limitations of "a controller having an input which receives a
bus permission signal and an output connected to said runaway
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