Appeal No. 1999-2256 Page 15
Application No. 08/686,477
have suggested the limitations of “issuing a bus permission
signal by the CPU [and] receiving the bus permission signal by
the watch dog timer and the DMA controller” or “a bus
permission line, different from the control bus, connected
between the CPU, the DMA controller, and the watch dog timer
....” Therefore, we reverse the rejection of claim 11 and of
claims 12-15, which depend therefrom. We also reverse the
rejection of claim 16 and of claims 17-20, which depend
therefrom. We proceed to the last group of claims.
IV. Claims 22-24
The examiner asserts, “Richardson teaches the controller
halts the supplying of the clock signal to the counter when
the controller receives the bus permission signal [see the
hold signal, col. 2, lines 10, 11 ].” (Examiner’s Answer at
14.) The appellants argue, “there is no disclosure within
Richardson et al of the preventing of an outputting of the
reset signal ....” (Reply Br. at 7.)
In deciding anticipation, “the first inquiry must be into
exactly what the claims define.” In re Wilder, 429 F.2d 447,
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