Appeal No. 1999-2256 Page 2
Application No. 08/686,477
timer sets a time-out value for a program being executed by a
microprocessor-based system. When the program is operating
normally, a central processing unit (“CPU”) sends a signal via
the system’s bus to reset the timer before the latter
“overflows,” i.e., reaches the time-out value. When an
abnormality such as a program runaway occurs, in contrast, the
CPU does not reset the timer. Accordingly, the timer
overflows, and an overflow signal is transmitted to the CPU
and other devices in the system.
A problem occurs when using a watch dog timer in a
microprocessor-based system that includes a bus master such as
a direct memory access controller (“DMAC”). Specifically,
when the DMAC uses the system’s bus for a direct memory access
(“DMA”) transfer, the system’s CPU cannot use the bus to send
a reset signal, and the timer overflows.
According to the appellants’ invention, when a DMA
transfer is needed, the DMAC issues a request to the system’s
CPU. After processing the request, the CPU issues a bus
permission signal to both the watch dog timer and the DMAC.
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007