Appeal No. 1999-2683
Application 08/754,564
withdrawn pursuant to a restriction requirement. The
amendment (Paper No. 17) filed February 16, 1999, has not been
entered.
We reverse.
BACKGROUND
The invention relates to an integrated circuit, claimed
in structural and product-by-process format, having an etch
stop layer on top of the bottom metal lines and under the
interlayer dielectric (ILD) to prevent overetching during via
formation. Overetching can cause exploding misaligned vias
and trenching.
Claim 18 is reproduced below.
18. An integrated circuit having a plurality of
semiconductor devices therein and a multilevel
metallization structure for interconnection of said
semiconductor devices thereon, said multilevel
metallization structure comprising:
a plurality of substantially parallel, separated,
patterned metal layers including a first bottom metal
layer and a second top metal layer, said first bottom
metal layer being separated from said top metal layer by
an ILD layer therebetween, each of said patterned metal
layers being comprised of metal lines separated by gaps;
said ILD layer between said first bottom metal layer
and said second top metal layer having vias therethrough,
said vias having conducting via plugs therein, said via
plugs providing electrical connectivity between said
first metal bottom layer and said top metal layer;
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