Appeal No. 1999-2683
Application 08/754,564
overlying material being etched, its etch rate being
sufficiently lower so that the etch stop layer is
substantially unaffected during any necessary overetch.
Appellant also provides an addendum to the declaration of
Mr. Mehta (Paper No. 16) which states that "the relative etch
rate difference between CVD oxide [layer 24] and SOG [layer 26
in Tsu] is approximately 2:1 or less" (para. 5) based on U.S.
Patent 5,173,151, issued December 22, 1992, to Namose, which
was cited by the Examiner. Mr. Mehta further declares
(para. 6):
6. To the best of my knowledge on information and
belief, for both the structures in Tsu and in the present
invention, a minimum etch rate difference of 4:1 between
the ILD and the underlying layer is required to
effectively use the underlying layer as a via etch stop
layer. It is well known in the art that standard dry
etch processes provide an etch rate selectivity of at
least 4:1 for silicon dioxide over silicon nitride.
Mr. Mehta also states (para. 7) that it was well known in the
art to use CVD layers (such as CVD oxide layer 24 in Tsu) as
chemical barriers to prevent contact between SOG and materials
such as resist and metal, citing the reference by Chu et al.
(Chu), Spin-on-Glass Dielectric Planarization for Double Metal
CMOS Technology, Proc. 1986 VMIC Conference, pp. 474-483.
Appellant explains that it is necessary to overetch, that
is, to employ an etch for a period longer than the calculated
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