Appeal No. 1999-2683
Application 08/754,564
said bottom metal layer having therein at least one
bottom metal line having a top conducting surface and an
edge surface, said bottom metal line being surrounded by
a dielectric layer having a top dielectric surface, said
top conducting surface and said top dielectric surface
being substantially locally coplanar near said bottom
metal line, a first portion of said top dielectric
surface not being coincident with said vias, and a first
portion of said top conducting metal surface not being
coincident with said vias;
said first portion of said top dielectric surface
not coincident and said first portion of said top
conducting metal surface not coincident having thereon a
thin non-conducting via etch-stop layer under said ILD.
The Examiner relies on the admitted prior art (APA) of
Appellant's figures 1 and 4 and following references:
Tsu 5,432,128 July 11,
1995
Kalnitsky EP 0 523 856 January 20,
1993
(European Patent Application)
Claims 18-32 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Tsu, Kalnitsky, and the APA. The
Examiner finds that Tsu discloses the structure of independent
claim 18 except "that it does not specifically disclose that a
thin oxide layer 24 in Fig. 3f is an etch-stop layer of
silicon nitride" (Final Rejection, p. 3). However, the
Examiner finds that silicon oxide layer 24 of Tsu is clearly
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