Ex parte SAKASHITA et al. - Page 1




          The opinion in support of the decision being entered today was not written for
                    publication and is not binding precedent of the Board.            

                                                            Paper No. 21              


                      UNITED STATES PATENT AND TRADEMARK OFFICE                       
                                    _____________                                     
                         BEFORE THE BOARD OF PATENT APPEALS                           
                                 AND INTERFERENCES                                    
                                    _____________                                     
                   Ex parte NARUMI SAKASHITA and KAZUTAMI ARIMOTO                     
                                    _____________                                     
                                Appeal No. 1999-1098                                  
                               Application 08/627,313                                 
                                   ______________                                     
                                      ON BRIEF                                        
                                   _______________                                    

          Before THOMAS, HAIRSTON, and FLEMING, Administrative Patent                 
          Judges.                                                                     
          FLEMING, Administrative Patent Judge.                                       


                                 DECISION ON APPEAL                                   
               This is a decision on appeal from the final rejection of               
          claims 1-13, all of the claims pending in the present                       
          application.                                                                
               The instant invention relates generally to semiconductor               
          memory devices with arrangements of memory blocks and                       
          peripheral circuits (specification, page 1, lines 6-9).                     
                                          1                                           





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