Appeal No. 1999-1098
Application 08/627,313
As regards the Examiner's argument that in a real layout
the spacing is made as small as possible in accordance with
known semiconductor design rules, we nevertheless find that as
there are no memory blocks at the right and left sides of the
peripheral circuit of figure 17, it is not completely
surrounded.
Turning to Seefeldt we find that this reference teaches
I/O peripheral circuits (32) intermingled with gate circuits
(31) wherein the I/O peripheral circuits reside at the center
of radially formed blocks. However, we find that Seefeldt is
replete with teachings to intermingle or interdistribute gate13
cells and I/O cells rather than surrounding the gate cells
with the I/O cells. Furthermore, the reason given by 14
Seefeldt for the intermingling is the improved routability
caused by locating the I/O cells close to the circuitry that
have been routed to perform a prescribed circuit function.
This is done to reduce interconnects between the cells and
global routing channels. This is not a reason to completely
13Column 2, lines 5-9; column 3, lines 46-62; column 5
lines 16-26 and 40-57; column 6, lines 4-14
14Column 6, lines 14
12
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