Appeal No. 1999-1098
Application 08/627,313
As regards claim 10, the Examiner adds the Ichiguchi
reference solely for its teaching of peripheral circuits
including address strobe buffering, read buffers, write
buffers and row and column decoders. As regards claim 12, The
Examiner adds the Katto reference solely for its teaching of
redundancy circuitry in memory cell arrays for correction of
bad cells. As these references are not relevant to our
decision above, the rejection of these dependent claims is
reversed for the reasons given above.
Therefore, based on the foregoing, we conclude that the
Examiner has failed to establish a prima facie case of
unpatentability under 35 U.S.C. § 103 with respect to claims
1-13.
Accordingly, we reverse the Examiner's rejection of
claims 1-12 under 35 U.S.C. § 103(a) as obvious over the
admitted prior art and Kusunoki and Seefeldt; the rejection of
claim 10 under
35 U.S.C. § 103(a) as obvious over the admitted prior art,
Kusunoki, Seefeldt and Ichiguchi; the rejection of claim 12
under 35 U.S.C. § 103(a) as obvious over the admitted prior
16
Page: Previous 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Next
Last modified: November 3, 2007