Appeal No. 1999-1098
Application 08/627,313
the specific arrangement of memory blocks and peripheral
circuits as claimed, and such arrangement addresses a
particular need in the art (providing substantially equal
signal delay between the peripheral circuit and the respective
memory blocks), the actual motivation for the Examiner's
proposed modification of the prior art to arrive at the
claimed invention is found in Appellants' disclosure.
As regards prior art figure 17, Appellants argue that 6
while a peripheral circuit might be interpreted to be located
at the center of the semiconductor substrate, it is not
completely surrounded by memory blocks since there are
openings between memory blocks MA1-MA4.
In addition, Appellants assert that the Examiner's sole7
basis as to why one skilled in the art would have been led by
the prior art as a whole to modify or combine the applied
prior art to arrive at the claimed invention is that it is a
simple design choice to arrange the cells and peripheral
circuits. This basis, Appellants argue, is not a logical
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