Appeal No. 1999-1098
Application 08/627,313
for arrangement of the cells and periphery therein."
(Emphasis added). Hereto, as Appellants have provided a
reason for the claimed arrangement, i.e., to reduce unequal
signal delays due to different path lengths, the Examiner must
provide evidence as to why one of ordinary skill in this art
would have selected the claimed arrangement of memory blocks
and peripheral circuits. No such evidence is of record.
Finally, as regards claim 13, the Examiner adds the Koike
reference and notes that it provides for an arrangement of17
blocks wherein the long sides of one block are adjacent short
sides of another block. The Examiner then finds "It would
have been obvious to a skilled artisan to combine the
teachings of Koike with the Prior Art Figs. 16-17, Kusunoki
and Seefeldt as a choice in design in order to optimize space
on the wafer as clearly taught by Koike."
First, we find that Koike provides the particular 18
circuit placement in order to reduce the minimum distance
between the terminals of the cells, a purpose different from
17Answer, page 6
18Column 4, lines 7-13
14
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