Appeal No. 2005-2512
Reexamination Control No. 90/006,431
3. Tiwary and Deng
Tiwary at page 87 explains that the author is a senior applications engineer at
Epic. The caption for Figure 3 describes it as a display generated by PowerMill, a
power management tool for detecting dc paths and other sources of power drain.
Figure 3 is not described as depicting a ChipViewer display and does not resemble the
RailMill ChipViewer displays depicted in Figures 14A and 14B of the ‘952 patent. Figure
4, on the other hand, closely resembles Figure 14A of the ‘952 patent and is
accompanied by the following caption: “Voltage drops in a static RAM power net are
made apparent by being displayed in different colors for different ranges of values.
Color and voltage range keys are at the bottom and the lower right. Power supply
inputs are at the left, top and bottom.” Tiwary also explains:
So, in deep submicron designs, voltage drop analysis is crucial [Fig. 4].
One way to perform power-net simulation is to divide a design into
two parts—a standard transistor circuit and a power network of extracted
supply voltage and ground nets. The transistor current information is
computed (assuming a constant supply voltage) and passed on to the
power-net simulator. The node voltages and branch currents thus
obtained can be used for checking voltage drops. Peak voltage drops can
be checked against user-specified thresholds. This gives designers a
quick way of identifying problem areas in their designs.
Tiwary 86 (brackets in original). Tiwary does not, however, mention RailMill.
The Deng article at page 3 likewise identifies its author as an employee of Epic.
The features of the PowerMill product are discussed at pages 3-7. At page 7, Deng
discusses a proposed two-step method for performing a power- net simulation:
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