Appeal No. 2005-2512
Reexamination Control No. 90/006,431
A two-step method has been proposed. In the first step, PowerMill
is applied to find currents flowing into the transistor blocks. PowerMill
assumes constant voltages at power buses during this step. Step two
simulates the power-bus network, modeled as an RLC network and driven
by current sources representing the simulated currents in step one.
Based on this scheme, a power-net reliability simulation package is being
developed and tested. It includes a layout extractor to model the power
net in terms of the extracted RLC parasitics, a power-net simulator to
simulate the RLC network driven by current sources estimated from
PowerMill simulation on the transistor blocks, and a layout display tool to
highlight the excessive current densities and voltage drops in the power
net. Figure 2 shows the voltage drop distribution in the power net.
Although the actual display separates voltage levels by color, they can be
distinguished here by shades of gray.
Deng at 7, cols. 1, 2 (footnote omitted). The image depicted in Figure 2 at page 7
closely resembles an image in the RailMill ChipViewer display depicted by Figure 14B of
the ‘952 patent, more particularly the image in chip layout display window 1406 of the
display. Deng, like Tiwary, makes no mention of RailMill.
Ho’s only discussion of the content of Tiwary and Deng is as follows:
6. . . . The Tiwary document describes work of Epic Design
Technology. I am informed that the Examiner has referred to page 86,
where images of a graphical user interface are shown. Because I have
never seen this article before, and was not consulted in the preparation of
the article, I do not know the origin of the images on page 86. However,
the images on page 86 appear to have been generated using ChipViewer.
7. . . . The [Deng] article describes the PowerMill product of Epic
Design Technology. I am informed that the Examiner has referred to
Figure 2, on page 7 of the article. Because I have never seen this article
before, and was not consulted in the preparation of the article, I do not
know the origin of the image in Figure 2. However, the image in Figure 2
appears to have been generated using ChipViewer.
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