Appeal No. 95-3658
Application 07/777,877
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134 from the final rejection of claims 1-8, 10-12,
and 16-17, all of the claims pending in the application. Claims 9, 13-15, and 18-19 have been cancelled.
The amendment received December 27, 1994 (Paper No. 12), has been entered and deemed to overcome
the rejection under 35 U.S.C. § 112, second paragraph (Supp. Examiner's Answer, Paper No. 14,
page 1).
The invention is directed to a memory array built in self test (ABIST) system for allocation of spare
or redundant column lines and row lines for unacceptable memory array column and row lines. As
disclosed, the ABIST is located on the semiconductor chip with the memory array. The ABIST has a first
number of registers equal to the number of redundant columns and a second number of registers equal to
the number of redundant rows. The columns are scanned sequentially and if more defects are found in the
rows of a column than there are redundant rows, that column address is stored or "locked in" to the register
for replacement. The rows are then scanned and columns whose addresses are in the first registers are
masked. Rows with defects in the visible column locations have addresses "locked in" to the row registers
until the number of row registers are filled and then any remaining empty column registers are used to store
the column address of the defect. The column and row addresses are scanned out and a redundancy
processor substitutes appropriate redundant column or row lines for faulty array column or row lines.
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