Appeal No. 95-3658
Application 07/777,877
substitution of columns and rows will be transparent. Stated differently, it would have been obvious to test
and program a chip with address registers such as Eaton with the testing system of Harns because Harns
is not limited to testing any particular type of memory device. The rejection does require physically shifting
structure from the test system of Harns on to the memory DUT.
For the reasons stated above, it is our opinion that a prima facie case of obviousness has been
established with respect to claim 1 and also with respect to claim 8, which is of the same scope because
the limitations of first and second pluralities of lines arranged orthogonally to each other is met by the
columns and rows shown in Harns.
Appellants argue that they "store addresses of failing lines in registers and not the bit location of a
failed cell in a second memory array" (Brief, page 9). Appellants assume that it is structure corresponding
to the BFRAM of Harns that the examiner proposes putting on the same semiconductor chip as the
memory (Brief, pages 9-10). However, the statements of the rejection in the Final Rejection and in the
Examiner's Answer discuss "registers" and "memory failure registers," generally, not the BFRAM. Harns
has column and row mask RAMs 171 and 172 that hold the addresses of columns and rows selected for
replacement and these RAMs correspond most closely to the first and second register means except that
they are not on the chip. The address replacement information in the RAMs of Harns is the information
that would be stored in the address circuitry of the memory chip of Eaton. It is not reasonable to consider
the BFRAM to be the row and column registers that are proposed to be mounted on the chip because:
(1) the BFRAM holds an image of the failure data, not addresses of the results of the row and column
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