Appeal No. 95-3658
Application 07/777,877
replacement algorithm on the failure data; (2) the BFRAM is structurally different from the address circuitry
in Eaton which is the structure the rejection proposes to be on the chip.
The examiner's response to the arguments (Examiner's Answer, pages 4-6) confuses rather than
clarifies the rejection. We have addressed the rejection as we understand it from the statement of the
rejection. We understand that the disclosed and claimed invention stores addresses of failed rows and
columns, not locations of stored cells (Reply Brief, pages 2-5). However, Harns discloses storing both the
location of stored bits in the two-dimensional BFRAM and the address of failed rows and columns in
RAMs 171 and 172. Appellants do not address the teaching of identifying defective columns and rows
in Harns. The examiner discusses that appellants' invention stores the address of the faulty cells in a two
dimensional failed address register and since the BFRAM is a two dimensional array this suggests that the
examiner proposes putting a BFRAM structure on the chip. It appears that the examiner may have been
confused by appellants' arguments about the BFRAM. The fact is that Harns identifies the addresses of
columns and rows selected for replacement in the same manner as the disclosed invention and the rejection
is that it would have been obvious to store these defective addresses in registers on the chip as taught by
Eaton. The fact that Harns uses a BFRAM to hold an image of the faulty cells as intermediate structure
in the test system for identifying faulty columns and rows is not precluded by claim 1.
Appellants discuss the structure disclosed in the specification corresponding to the various means
of claim 1 (Brief, page 11). However, appellants do not raise the question of claim interpretation under
35 U.S.C. § 112, sixth paragraph. We presume that the structures in Harns and Eaton that perform the
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