Appeal No. 95-3658
Application 07/777,877
Claim 1 is reproduced below.
1. An array built in self test (ABIST) system comprising
a single semiconductor chip,
a memory array disposed on said semiconductor chip having a plurality of column lines and
a plurality of row lines and at least one redundant column line and at least one redundant row line
with cells coupled to the lines at intersections thereof,
first means coupled to said memory array for identifying a given number of faulty cells along
each of said column lines,
first register means disposed on said semiconductor chip having a number of registers equal
to the number of redundant column lines,
means for applying column address signals to said first register means,
means coupled to said first identifying means for storing the address signals of each of the
column lines having said given number of faulty cells in said first register means,
second means coupled to said memory array for identifying a faulty cell along each of said
row lines while masking the faulty cells having address signals of said column lines stored in said
first register means,
second register means disposed on said semiconductor chip having a number of registers
equal to the number of redundant row lines,
means for applying row address signals to said second register means,
means coupled to said second identifying means for storing the address signals of each of
the row lines having a faulty cell in said second register means until said second register means is
filled to capacity and then storing the column line address signals of any additional faulty cells
identified in said row lines in said first register means, and
means coupled to said registers for substituting said redundant column and row lines for
the column and row lines having address signals stored in said first and second register means.
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Last modified: November 3, 2007