Ex parte HEDBERG et al. - Page 11




              Appeal No. 95-3658                                                                                                                          
              Application 07/777,877                                                                                                                      

              claimed functions are equivalent under 35 U.S.C.  112, sixth paragraph, absent argument to the contrary.                                   

              See Guidelines, 1162 Off. Gaz. Pat. & Trademark Office at 59-60.  Limitations of the disclosed structure                                    

              are not read into the claims.  For example, although the first identifying means is disclosed to be a data                                  

              compression circuit on the chip the claim recites only that the first identifying means is "coupled to said                                 

              memory array," which does not require the means to be on the chip.                                                                          

                       Appellants argue (Brief, pages 11-12):                                                                                             

                       Neither Harns nor EAton [sic], Jr., et al, nor the combination thereof, teach a test system located                                
                       on the same semiconductor chip with the device or memory under test wherein column addresses                                       
                       are applied to a register located on the memory chip and stored or locked therein when means                                       
                       identify a given plurality of faulty cells along a given column line and row addresses are applied to                              
                       another register also located on the same chip and stored or locked therein when means identify                                    
                       a faulty cell when scanning the memory along a given row.                                                                          

              Claim 1 does not require the whole test system to be located on the same semiconductor chip.  Only those                                    

              means expressly recited to be on the chip are required to be on the chip, i.e., the memory array and the                                    

              first and second register means.  Claim 1 also does not recite locking an address into a register when (in                                  

              the time sense of immediately after) means identify a given number of faulty cells as suggested by appellants'                              

              argument.  The claimed "means . . . for storing the address signals" could store the addresses after the                                    

              whole testing process is finished, although this interpretation is not at issue.                                                            

                       Appellants' arguments do not rebut the prima facie case of obviousness.  Accordingly, the rejection                                

              of claims 1 and 8 is sustained.                                                                                                             




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