Appeal No. 95-3658
Application 07/777,877
Answer, page 3). We agree. The examiner's response to the arguments confuses rather than simplifies the
rejection in terms of what modification is being proposed and will be discussed later.
Eaton describes that the addresses of defective main rows and column lines are stored or
programmed in fuse circuitry in the RAM during probe testing (e.g., column 2, line 62 to column 3, line 6).
This circuitry is equivalent to the claimed first and second register means because it stores addresses
electronically. Structures in Harns and Eaton that perform the claimed functions are presumed to be
equivalent to structures disclosed to correspond to the claimed means under 35 U.S.C. § 112, sixth
paragraph, absent argument to the contrary. See Examination Guidelines for Claims Reciting a Means or
Step Plus Function Limitation In Accordance With 35 U.S.C. § 112, 6th Paragraph, 1162 Off. Gaz. Pat.
& Trademark Office 59, 59-60 (May 17, 1994) (Guidelines). Manifestly, Eaton must have structure for
applying the column and row addresses from the testing system to the address stores. The spare column
decoders (SCD) and spare row decoders (SRD) in Eaton are coupled to the address storing circuitry and
function to substitute spare columns and spare rows (column 2, line 62 to column 3, line 19). Thus, the
SCD and SRD and their accompanying circuitry in Eaton constitute "means coupled to said registers for
substituting said redundant column and row lines" (claim 1). Harns has column and row mask RAMs 171
and 172 that hold the addresses of columns and rows selected for replacement according to the broad
algorithm recited in claim 1. It would have been obvious to the artisan to substitute a chip such as Eaton
for the memory DUT in Harns and to store the addresses of defective columns and rows from Harns in the
chip address circuitry because such chips require the addresses of defective columns and rows so that
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