Appeal No. 95-3658
Application 07/777,877
register means," "means for applying row address signals," and "means . . . for storing the address signals
. . . in said second register means until said second register means is filled to capacity and then storing the
column line address signals . . . in said first register means" to be on the chip. Only the memory array and
the first and second register means are expressly claimed as being "disposed on said semiconductor chip."
Importantly, claim 1, as interpreted, does not require the column and row address signals to be
stored or "locked in" as the column and rows are being tested. The claimed "means . . . for storing the
address signals" does not state when the address signals are stored, which broadly leaves open the
interpretation that the address signals can be stored in the on-chip registers after the testing is all complete
(as in Eaton). The "means coupled to said registers for substituting said redundant column and row lines"
is not limited to laser fuse blowing circuitry which blows fuses in response to addresses stored in the
registers as disclosed (e.g., specification, page 8) and broadly encompasses circuitry for substituting column
and row lines in response to the stored addresses (e.g., the spare column decoder and spare row decoder
circuitry in Eaton which accesses spare columns and spare rows). Claim 1 does not capture the "real time"
aspect of the disclosed circuitry where the logic circuitry cooperates with the registers and the data
comparison circuitry to lock the addresses into the registers during testing.
The examiner finds that Eaton discloses storing the defective row and column addresses in stores
on the same chip as the memory array and concludes that this would have suggested to the artisan placing
memory failure registers on the same chip as the memory array (Final Rejection, page 2; Examiner's
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