Appeal No. 95-3658
Application 07/777,877
address, a store for a defective column address, and a comparator. "The stores retain defective memory
cell addresses which the comparator sequentially compares against the address data sequentially output
by the buffer. When the comparator senses a match, a control signal is generated to initiate substitution of
spare memory cells for the defective main memory cells." (Abstract.)
Claims 1-8, 10-12, and 16-17 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Harns and Eaton. The examiner finds that "Harns does not teach having a first and second register to hold
the address of the faulty row/columns located on the same chip as the memory array" (Final Rejection, page
2; see also Examiner's Answer, page 3). The examiner finds that Eaton discloses storing the defective row
and column addresses in stores on the same chip as the memory array and concludes that this would have
suggested to the artisan placing memory failure registers on the same chip as the memory array (Final
Rejection, page 2; Examiner's Answer, page 3).
OPINION
We affirm-in-part.
The level of ordinary skill is not argued, so we find the references to be representative of the level
of skill in the art. See In re Oelrich, 579 F.2d 86, 91, 198 USPQ 210, 214 (CCPA 1978) ("the PTO
usually must evaluate both the scope and content of the prior art and the level of ordinary skill solely on the
cold words of the literature"). Cf. Chore-Time Equipment Inc. v. Cumberland Corp., 713 F.2d 774, 779
n.2, 218 USPQ 673, 676 n.2 (Fed. Cir. 1983) ("We hold only that an invention may be held to have been
obvious (or nonobvious) without a specific finding of a particular level of skill in the art where, as here, the
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