Appeal No. 95-3658
Application 07/777,877
The examiner relies on the following references:
Eaton, Jr. et al. (Eaton) 4,389,715 June 21, 1983
Harns 4,460,997 July 17, 1984
Harns discloses a memory tester for testing chips having a memory array with redundant rows and
columns. As shown in figure 1, a memory device under test (DUT) is connected to a pin electronics and
error detection board 14. A programmable pattern generator 25 provides address, clock, and signals for
comparison for exercising and testing the memory DUT. An error capture and analysis system 31 (figure
2) provides memory repair analysis capability and has two main modes of operation described at column 5,
lines 16-49. In a first test mode, the DUT 13 is tested under programmable pattern generator 25 control
and the resultant failure data is stored in a bit fail random access memory (BFRAM) 49. The BFRAM 49
is configured to correspond to one of the different memory matrix configurations under test (column 6,
lines 33-36). In a second mode of operation, post processing logic circuit 70 in system 31 processes the
error data to determine the repairability of the memory DUT as described at column 5, lines 23-49 and
column 18, line 50 to column 19, line 14. "The post processing logic circuit includes a row mask ram and
a column mask ram which stores the addresses of rows and columns which are masked for replacement"
(column 9, lines 61-64; see also column 14, lines 16-22).
Eaton discloses a RAM with spare rows and columns of memory cells to provide redundancy. The
RAM includes a plurality of address buffers. Associated with each buffer is a store for a defective row
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