Appeal No. 96-1426
Application 08/001,863
DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134 from the rejection of claims 1, 3, 6, and
7, which constitute all the claims pending in the application. Claims 2, 4, and 5 have been
cancelled.
The invention is directed to a method and system for eliminating data dependency hazards
in a superscalar computer which includes instructions having a greater number of source operands
than may be interlocked utilizing a data dependency interlock circuit. Data dependency hazards
occur, for example, when a first instruction must write its result (to a destination operand) before
the second instruction can read and subsequently use the result (as a source operand). To allow
this write before read, execution of the read must be blocked until the write has occurred; that is,
there is an "interlock" between the write and read instructions, specifically between the destination
operand and the source operand. Modern superscalar machines use "data dependency interlock
circuits" which "contain logic which operates in concert with instruction dispatch circuitry to
ensure that an instruction is not dispatched until such time as a result from a preceding instruction
which is necessary for correct execution of that instruction has been obtained" (specification,
page 3). It is common in existing superscalar machines to use a source-to-destination interlock
circuit "which is capable of interlocking two source operands with two destination operands, to
ensure that data dependency hazards for such operands clear prior to permitting dispatch of an
instruction containing these operands" (specification, page 9). To use an instruction with three
operands would require a proportional increase in the logic required to implement a data
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