Ex parte KAHLE et al. - Page 10

        Appeal No. 96-1426                                                              
        Application 08/001,863                                                          

             instructions (e.g. see NR r1,r2 and S r3,D(R4,R5) in col.16,               
             lines 35-36; see also the AGI0-3 of the source operands)                   
             which include more than N source operands were collapsed                   
             (e.g. see col.15, lines 64-68; col.16, lines 1-9) using the                
             interlock collapsing ALU (see also branch hazard-collapsing                
             ALU for instructions BCT and AL which had more than N                      
             operands in col.17, lines 24-27).                                          
        The examiner errs in finding this limitation to be disclosed.                   
        First, the data dependency collapsing ALU in Vassiliadis is not                 
        "source-to-destination dependency interlock circuitry" because it               
        does not interlock instructions:  it eliminates interlocks                      
        between instructions.  Thus, Vassiliadis does not disclose                      
        "elimination of possible data dependency hazards for a first N                  
        source operands, as indicated by said source-to-destination                     
        dependency interlock circuitry" for an "instruction which                       
        includes more than N source operands."  Second, Vassiliadis does                
        not disclose instructions having more source operands than can be               
        interlocked with "source-to-destination dependency interlock                    
        circuitry."  The data dependency collapsing ALU is not interlock                
        circuitry and it eliminates all data dependencies between two                   
        instructions, not just some.  Thus, Vassiliadis does not disclose               
        eliminating data dependency hazards for N source operands with                  
        "source-to-destination  dependency  interlock  circuitry"  and                  
        thereafter awaiting execution of all previous instructions prior                
        to execution of the remaining instruction operands.  Third, the                 

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