Appeal No. 96-1426
Application 08/001,863
(e.g., specification, page 3) and the "source-to-destination
dependency interlock circuitry" in claim 1. Vassiliadis's
invention does not deal with this interlock hardware, nor does
the examiner rely on the hardware in the background of the
invention. Nevertheless, because such hardware for interlocking
N source operands is described in the background of Vassiliadis
and is admitted by appellants to be well known (specification,
page 3), we find that the limitation of "dispatching each scalar
instruction . . . which includes no more than N source operands
upon elimination of possible data dependency hazards, as
indicated by said source-to-destination dependency interlock
circuitry" to be disclosed.
As to the limitation of "dispatching each scalar instruction
which includes more than N source operands only upon elimination
of possible data dependency hazards for a first N source
operands, as indicated by said source-to-destination dependency
interlock circuitry and a completion of all preceding
instructions," the examiner finds (Examiner's Answer, page 3):
b)each scalar instruction (e.g. S r3,D(R4,R5) in
col.16, line 36; see also S R3,D(R4,R1) in (5) and
S R3,D(R1,R5) in (4); see fig.2 for scalar instructions)
which includes more than N source operands (R4,R5,D) only
upon elimination of possible hazards for first N sources
(r4,r5) (e.g. see col.16, lines 37-65; see the detection of
r4 or r5 with r1) as detected by the interlock circuitry
[ALU], wherein possible data dependencies for scalar
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